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ASAHI KASEI
[AK4355]
AK4355
192kHz 24-Bit 6ch DAC for DVD-Audio
GENERAL DESCRIPTION The AK4355 offers the perfect mix for cost and performance based multi-channel audio systems. AKM's advanced multi-bit architecture delivers a wide dynamic range and low outband noise. The AK4355 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of application including DVD-Audio. FEATURES o Sampling Rate: 8kHz to 192kHz o 24Bit 8 times Digital Filter with Slow roll-off option o THD+N: -90dB o DR, S/N: 106dB o High Tolerance to Clock Jitter o Low Distortion Differential Output o Digital De -emphasis for 32, 44.1 & 48kHz sampling o Zero Detect Pin o Channel Independent Digital Attenuator with soft-transition o Soft Mute 2 o I/F format: 24-Bit MSB justified, 24/20/16 -Bit LSB justified or I S o Master Clock Normal Speed: 256fs, 384fs, 512fs or 768fs Double Speed: 128fs, 192fs, 256fs or 384fs Quad Speed: 128fs, 192fs o Power Supply: 4.75 to 5.25V o 28pin VSOP Package
DZF LOUT1+ LOUT1ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
SCF
DAC
DATT
Audio I/F
AK4355
MCLK LRCK
SCF
DAC
DATT
BICK
SCF
DAC
DATT DATT
Control Register
CSN CCLK CDTI
SCF
DAC
SCF
DAC
DATT DATT
SDTI1 SDTI2 SDTI3
SCF
DAC
MS0063-E-01 - 1-
2002/07
ASAHI KASEI
[AK4355]
n Ordering Guide
AK4355VF AKD4355 -40 +85C 28pin VSOP (0.65mm pitch) Evaluation Board for AK4355
n Pin Layout
VREF DZF PDN MCLK BICK SDTI1 SDTI2 SDTI3 LRCK CSN CCLK CDTI DVDD DVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
AVDD AVSS LOUT1+ LOUT1ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
Top View
23 22 21 20 19 18 17 16 15
MS0063-E-01 - 2-
2002/07
ASAHI KASEI
[AK4355]
PIN/FUNCTION
Function Positive Voltage Reference Input Pin Zero Input Detect Pin Power-Down Mode Pin When at "L", the AK4355 is in the power-down mode and is held in reset. The AK4355 should always be reset upon power-up. 4 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 5 BICK I Audio Serial Data Clock Pin 6 SDTI1 I DAC1 Audio Serial Data Input Pin 7 SDTI2 I DAC2 Audio Serial Data Input Pin 8 SDTI3 I DAC3 Audio Serial Data Input Pin 9 LRCK I L/R Clock Pin 10 CSN I Chip Select Pin 11 CCLK I Control Clock Pin 12 CDTI I Control Data Input Pin 13 DVDD Digital Power Supply Pin 14 DVSS Digital Ground Pin 15 ROUT3O DAC3 Rch Negative Analog Output Pin 16 ROUT3+ O DAC3 Rch Positive Analog Output Pin 17 LOUT3O DAC3 Lch Negative Analog Output Pin 18 LOUT3+ O DAC3 Lch Positive Analog Output Pin 19 ROUT2O DAC2 Rch Negative Analog Output Pin 20 ROUT2+ O DAC2 Rch Positive Analog Output Pin 21 LOUT2O DAC2 Lch Negative Analog Output Pin 22 LOUT2+ O DAC2 Lch Positive Analog Output Pin 23 ROUT1O DAC1 Rch Negative Analog Output Pin 24 ROUT1+ O DAC1 Rch Positive Analog Output Pin 25 LOUT1O DAC1 Lch Negative Analog Output Pin 26 LOUT1+ O DAC1 Lch Positive Analog Output Pin 27 AVSS Analog Ground Pin 28 AVDD Analog Power Supply Pin Note: All input pins should not be left floating. No. 1 2 3 Pin Name VREF DZF PDN I/O I O I
MS0063-E-01 - 3-
2002/07
ASAHI KASEI
[AK4355]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog Digital |AVSS-DVSS| (Note 2) Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Symbol A VDD DVDD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V mA V V C C
Note: 1. All voltages with respect to ground. 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital Voltage Reference Note: Symbol A VDD DVDD VREF min 4.75 4.75 AVDD-0.5 typ 5.0 5.0 max 5.25 5.25 AVDD Units V V V
1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0063-E-01 - 4-
2002/07
ASAHI KASEI
[AK4355]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD, DVDD=5V; VREF=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; R L 4k ; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) THD+N fs=44.1kHz 0dBFS -90 -86 dB BW=20kHz -60dBFS -42 dB fs=96kHz 0dBFS -88 -84 dB BW=40kHz -60dBFS -39 dB fs=192kHz 0dBFS -86 dB BW=40kHz -60dBFS -39 dB Dynamic Range (-60dBFS with A-weighted) (Note 5) 100 106 dB S/N (A-weighted) (Note 6) 100 106 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C 3.0 3.2 3.4 Output Voltage (Note 7) Vpp Load Resistance (Note 8) 4 k Power Supplies Power Su pply Current (AVDD+DVDD) Normal Operation (PDN = "H", fs 96kHz) 49 75 mA Normal Operation (PDN = "H", fs=192kHz) 55 80 mA Power-Down Mode (PDN = "L") (Note 9) 10 100 A Notes: 4. Measured by Audio Precision (System Two) or UPD. Refer to the evaluation board manual. 5. 100dB at 16bit data. 6. S/N does not depend on input bit length. 7. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF, AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=3.2Vpp x VREF/5. 8. For AC-load. 4k for DC-load. 9. All digital inputs including clock pins (MCLK, BICK and LRCK) are held DVDD or DVSS.
MS0063-E-01 - 5-
2002/07
ASAHI KASEI
[AK4355]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75 5.25V; fs = 44.1kHz; DEM = OFF; SLOW="0") Parameter Symbol min typ max Units Digital filter 0.05dB (Note 10) Passband PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 10) SB 24.25 kHz 0.02 Passband Ripple PR dB Stopband Attenuation SA 54 dB Group Delay (Note 11) GD 20.5 1/fs Digital Filter + LPF 0.2 Frequency Response 20.0kHz fs=44.1kHz FR dB 0.3 40.0kHz fs=96kHz FR dB 80.0kHz fs=192kHz FR +0/ -0.6 dB Notes: 10. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535xfs (@ 0.05dB), SB=0.546xfs. 11. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the outpu t of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "1") Parameter Digital Filter Passband Stopband Passband Ripple Stopband Attenuation Group Delay Di gital Filter + SCF FR FR FR Note: 12. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs. 20.0kHz 40.0kHz 80.0kHz Frequency Response fs=44.kHz fs=96kHz fs=192kHz +0/ -5 +0/ -4 +0/ -5 dB dB dB (Note 11) 0.04dB -3.0dB (Note 12) SB PR SA GD 72 20.5 (Note 12) PB 0 39.2 18.2 8.1 0.005 kHz kHz KHz DB DB 1/fs Symbol min Typ max Units
DC CHARACTERISTICS
(Ta=25C; AVDD, DVDD = 4.75 5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-80A) Low-Level Output Volt age (Iout=80A) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 2.2 DVDD-0.4 Typ max 0.8 0.4 10 Units V V V V A
MS0063-E-01 - 6-
2002/07
ASAHI KASEI
[AK4355]
SWITCHING CHARACTERISTICS
(Ta=25C; AVDD, DVDD = 4.75 5.25V; CL=20pF) Parameter Master Clock Frequency Duty Cycle Symbol fCLK dCLK min 2.048 40 typ 11.2896 max 36.864 60 48 96 192 55 Units MHz % kHz kHz kHz %
LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 60 Quad Speed Mode fsq 120 Duty Cycle Duty 45 Audio Interface Timing BICK Period Normal Speed Mode tBCK 1/128fs Double/Quad Speed Mode tBCK 1/64fs BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 BICK rising to LRCK Edge (Note 13) tBLR 20 LRCK Edge to BICK rising (Note 13) tLRB 20 SDTI Hold Time tSDH 20 SDTI Setup Time tSDS 20 Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN "H" Time tCSW 150 CSN " " to CCLK " " tCSS 50 CCLK " " to CSN " " tCSH 50 Reset Timing PDN Pulse Width (Note 14) tPD 150 Notes : 13. BICK rising edge must not occur at the same time as LRCK edge. 14. The AK4355 can be reset by bringing PDN= "L".
ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns
MS0063-E-01 - 7-
2002/07
ASAHI KASEI
[AK4355]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
tBCK VIH VIL tBCKH tBCKL
LRCK
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tSDS tSDH VIH
SDTI
VIL
Serial Interface Timing
MS0063-E-01 - 8-
2002/07
ASAHI KASEI
[AK4355]
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0063-E-01 - 9-
2002/07
ASAHI KASEI
[AK4355]
OPERATION OVERVIEW n System Clock
The external clocks, which are required to operate the AK4355, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = "0": Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2~4). In Auto Setting Mode (ACKS = "1": Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS0/1. All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4355 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4355 may draw excess current may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4355 should be reset by PDN= "L" after threse clocks are provided. If the external clocks are not present, the AK4355 should be in the power-down mode (PDN= "L"). After exiting reset at power-up etc., the AK4355 is in the power-down mode until MCLK and LRCK are input.
DFS1 0 0 1
DFS0 0 1 0
Sampling Rate (fs) Normal Speed Mode Double Speed Mode Quad Speed Mode 8kHz~48kHz 60kHz~96kHz 120kHz~192kHz Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
768fs 24.5760MHz 33.8688MHz 36.8640MHz
BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK fs 88.2kHz 96.0kHz
128fs 11.2896MHz 12.2880MHz
MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
384fs 33.8688MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK fs 176.4kHz 192.0kHz
MCLK 128fs 22.5792MHz 24.5760MHz 192fs 33.8688MHz 36.8640MHz
BICK 64fs 11.2896MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MS0063-E-01 - 10 -
2002/07
ASAHI KASEI
[AK4355]
MCLK 512fs 256fs 128fs 768fs 384fs 192fs
Sampling Speed Normal Double Quad
Table 5. Sampling Speed (Auto Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
192fs 33.8688 36.8640
MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 -
512fs 16.3840 22.5792 24.5760 -
768fs 24.5760 33.8688 36.8640 -
Sampling Speed
Normal Double Quad
Table 6. System Clock Example (Auto Setting Mode)
n Audio Serial Interface Format
Data is shifted in via these SDTI1, SDTI2,and SDTI3 pins using BICK and LRCK inputs.The DIF0-2 as shown in Table 7 can select five serial data modes . In all modes the serial data is MSB-first, 2 's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 SDTI Format 16bit LSB Justified 20bit LSB Justified 24bit MSB Justified 24bit I2S Compatible 24bit LSB Justified BICK 32fs 40fs 48fs 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2
Default
Table 7. Audio Data Formats
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDTI Mode 0
0
15 14
1
6
14
5
15
4
16
3
17
2
1
31
0
0
15 14
1
6
14
5
15
4
16
3
17
2
1
31
0
15 14
0 1
BICK (64fs) SDTI Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing MS0063-E-01 - 11 -
Rch Data
2002/07
ASAHI KASEI
[AK4355]
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDTI Mode 1 SDTI Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1,4 Timing
Rch Data
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
MS0063-E-01 - 12 -
2002/07
ASAHI KASEI
[AK4355]
n De -emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
n Output Volume
The AK4355 includes channel independent digital output volumes (ATT) with 256 levels including MUTE and 0.5dB step . These volumes are in front of the DAC and can attenuate the input data from 0dB to -127dB and mute. Transition time is set by AST1-0 bits(Table10).In Mode0 and Mode1, when changing levels, transitions are exe cuted via soft changes; thus no switching noise occurs during these transitions. ATT7-0 FFH FEH FDH : 02H 01H 00H Attenuation Level 0dB -0.5dB -1.0dB : -126.5dB -127.0dB MUTE (- )
Default
Table 9. Attenuation Level of Output Volume Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 7424/fs 1061/fs 256/fs Reserved
Default
Table 10. Transition time of output volume In case of Mode0, it takes 7424/fs(168ms@fs=44.1k) to transit from FFH(0dB) to 00H(MUTE). In case of Mode1, it takes 1061/fs(24ms@fs=44.1k) to transit from FFH(0dB) to 00H(MUTE). In case Mode2 and 3,it takes 256/ fs(6ms@fs=44.1k) to transit from FFH(0dB) to 00H (MUTE). If PDN pin goes to "L", ATT7-0 registers are initialized to FFH.ATTN7-0 registers go to FFH when RSTN bit is set to "0". When RSTN bit returns to "1", ATT7-0 registers go to the set value. Digital output volume function is independent of soft mute function.
MS0063-E-01 - 13 -
2002/07
ASAHI KASEI
[AK4355]
n Zero Detection
When the input data atall channel is continuously zero s for 8192 LRCK cycles, DZF pin goes to "H". DZF pin immediately goes to " L" if input data of each channel is not zero after going DZF "H". If RSTN bit is "0", DZF pin goes to "H". DZF pin goes to " L" at 4~5LRCK if input data of each channel is not zero after RSTN bit returns to " 1". Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always "L". DZFB bit can invert the polarity of DZF pin. When one of PW1-3 bit is set to"0", the input data of DAC which the PW bit is set to "0" should be zero in order to enable zero detection of the other channels . When all PW1-3 bits are set to "0", DZF pin fixes "L".
n Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to"1", the output sig nal is attenuated by - during 1024 LRCK cycles. When the SMUTE bit is returned to "1", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE pin 1024/fs 0dB Attenuation (1) (3) 1024/fs
-
GD (2) AOUT GD
DZF pin
(4) 8192/fs
Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin immediately goes to "L" if input data are not zero after going DZF "H". Figure 5. Soft Mute and Zero Detection
MS0063-E-01 - 14 -
2002/07
ASAHI KASEI
[AK4355]
n System Reset
The AK4355 should be reset once by bringing PDN= "L" upon power-up. The AK4355 is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK4355 is in the power-down mode until MCLK and LRCK are input.
n Power-down
The AK4355 is placed in the power-down mode by bringing PDN pin "L" and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up. Each DAC can be powered down by each power-down bit (PW1-3) "0". In this case, the internal register values are not initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if the click noise influences system application.
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, LRCK, BICK
(3) (4)
(2)
(3)
(1)
Don't care
DZFL/DZFR External MUTE
(6)
(5)
Mute ON
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (4) The ext ernal clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = "L"). (5) Please mute the analog output externally if the click noise (3) influences system application. The timing example is shown in this figure. (6) DZF pins are "L" in the power-down mode (PDN = "L"). Figure 6. Power-down/up Sequence Example
MS0063-E-01 - 15 -
2002/07
ASAHI KASEI
[AK4355]
n Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to AVDD/2 voltage and DZF pin goes to "H". Figure 7 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZF Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to AVDD/2. (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = "L"). (5) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 2/fs after RSTN bit becomes "1". (6) There is a delay, 3~4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2~3/fs from RSTN bit "1" to the internal RSTN "1". Figure 7. Reset Sequence Example
MS0063-E-01 - 16 -
2002/07
ASAHI KASEI
[AK4355]
n Mode Control Interface
Internal registers may be written by 3-wire P interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to " 11"), Read/Write (1bit; fixed to "1", Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4355 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN "". The clock speed of CCLK is 5MHz (max). PDN = "L" resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "11") READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 8. Control I/F Timing *AK4355 does not support the read command and chip address. C1/0 and R/W are fixed to "111" *When the AK4355 is in the power down mode (PDN = "L") or the MCLK is not provided, writing into the control register is inhibited.
n Register Map
Addr Register Name 00H Control 1 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Notes: For addresses from 0BH to 1FH, data must not be written. When PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes to "0", the internal timing is reset, DZF pin go to "H" but registers are not initialized to their default values. Control 2
Speed & Control Power Down
D7 ACKS 0 0 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0
D6 SLOW 0 0 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0
D5 0 0 DFS1
0
D4 DZFE 0 DFS0
0
D3 DIF2 0 PW3
0
D2 DIF1 0 PW2
0
D1 DIF0
SMUT E
D0 RSTN RSTN RSTN
DEM0
PW1
DEM1
De-emphasis Control LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Control 3
ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0
ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 0
ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 0
ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DZFB
ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATS1
ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATS0
MS0063-E-01 - 17 -
2002/07
ASAHI KASEI
[AK4355]
n Register Definitions
Addr Register Name 00H Control 1 Default D7 ACKS 1 D6 SLOW 0 D5 0 0 D4 DZFE 1 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1
RSTN: Internal timing reset 0: Reset. DZF pin goes to "H" and registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4355 should be reset by PDN pin or RSTN bit. DIF2-0: Audio data interface modes (See Table 7) Initial: "010", Mode 2 DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit. SLOW: Slow roll-off response enable 0: Disable 1: Enable ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 are ignored. When this bit is "0", DFS1-0 set the sampling speed mode.
Addr Register Name 01H Control 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1
SMUT E
D0 RSTN 1
0
RSTN: Internal timing reset 0: Reset. DZF pin goes to "H" and registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4355 should be reset by PDN pin or RSTN bit. SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft -muted
MS0063-E-01 - 18 -
2002/07
ASAHI KASEI
[AK4355]
Addr Register Name 02H
Speed & Control Power Down
D7 0 0
D6 0 0
D5 DFS1 0
D4 DFS0 0
D3 PW3 1
D2 PW2 1
D1 PW1 1
D0 RSTN 1
Default
RSTN: Internal timing reset 0: Reset. DZF pin goes to "H" and registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4355 should be reset by PDN pin or RSTN bit. PW3-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 All sections are powered-down by PW1=PW2=PW3=0. DFS1-0: Sampling speed control (See Table 1) 00: Normal speed 01: Double speed 10: 4 times speed
Addr Register Name 03H De-emphasis Control Default
D7 0 0
D6 0 0
D5
0
D4
0
D3
0
D2
0
D1
DEM1
D0
DEM0
0
0
0
0
0
1
DEM1-0: De-emphasis response control for DAC1/2/3 data on SDTI1/2/3/ (See Table 8) Initial: "01", OFF
Addr 04H 05H 06H 07H 08H 09H
Register Name LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Default
D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 1
D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 1
D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 1
D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 1
D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 1
D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 1
D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 1
D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 1
ATT7-0: Attenuation Level 256 levels, 0.5dB step (See Table 9)
Addr Register Name 0AH Control 3 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 DZFB 0
D1 ATS1 0
D0 ATS0 0
ATS1-0: DATT Speed Setting (See Table 10) Initial: "00", mode 0 DZFB: Inverting Enable of DZF 0: DZF goes "H" at Zero Detection 1: DZF goes "L" at Zero Detection
MS0063-E-01 - 19 -
2002/07
ASAHI KASEI
[AK4355]
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4355) is available in order toallow an easy study on the layout of a surrounding circuit.
10u 0.1u + 0.1u 1 2 VREF DZF PDN MCLK BICK SDTI1 SDTI2 SDTI3 LRCK CSN CCLK CDTI DVDD DVSS AVDD AVSS LOUT1+ LOUT128 27 26 25 24
Analog 5V
Reset Master Clock 64fs 24bit Audio Data 24bit Audio Data 24bit Audio Data fs Microcontroller
3 4 5 6 7 8 9 10 11 12 10u + 0.1u 13 14
LPF
MUTE
L1ch Out R1ch MUT Out L2ch Out R2ch Out L3ch Out R3ch Out Digital 5V
AK4355
ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
LPF
23 22 21 20
MUTE
LPF
MUTE
LPF
19 18 17 16 15
MUTE
LPF
MUTE
LPF
MUTE
Digital Ground
Analog Ground
Figure 9. Typical Connection Diagram Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins should not be left floating.
MS0063-E-01 - 20 -
2002/07
ASAHI KASEI
[AK4355]
Digital Ground
Analog Ground
1 2 3 4 VREF DZF PDN MCLK BICK SDTI1 SDTI2 SDTI3 LRCK CSN CCLK CDTI DVDD DVSS AVDD AVSS LOUT1+ LOUT128 27 26 25 24 23 22 21 20 19 18 17 16 15
System Controller
5 6 7 8 9 10 11 12 13 14
AK4355
ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
Figure10. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4355 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4355 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be near to the AK4355 as possible, with the sm value ceramic capacitors being the nearest. all
2. Voltage Reference Inputs
VREF sets the analog output range. VREF pin is normally connected to AVDD with a 0.1F ceramic capacitor. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the AK4355
3. Analog Outputs
The analog outputs are full -differential outputs and 0.64 x VREFH Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, VAOUT =(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 6.4Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit). The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. DC offset on AOUT+/ - is eliminated without AC coupling since the analog outputs are differential. Figure 11and 12 show the example of external op-amp circuit summing the differential outputs.
MS0063-E-01 - 21 -
2002/07
ASAHI KASEI
[AK4355]
4.7k
4.7k R1 470p
AOUT-
Vop
3300p 4.7k R1
AOUT+
Vop
1k
Analog Out
4.7k
470p
BIAS
47u
0.1u When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
1k
Figure 11 External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k
4.7k R1 470p
AOUT-
+Vop
3300p 4.7k R1
AOUT+
Analog Out
-Vop
4.7k
470p
When R1=200 fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz When R1=180 fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 12 External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0063-E-01 - 22 -
2002/07
ASAHI KASEI
[AK4355]
PACKAGE
28pin VSOP (Unit: mm)
0.675 28 *9.8 0.2 1.25 0.2
15 *5.60.2 A 7.60.2 +0.1 0.15-0.05 0.10.1 Detail A 0.50.2 Seating Plane 0.10 0-10
2002/07 - 23 -
1 0.220.1
14 0.65
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0063-E-01
ASAHI KASEI
[AK4355]
MARKING
AKM AK4355VF
XXXBYYYYC
XXXXBYYYYC date code identifier XXXB: YYYYC: Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number, C : Alpha character)
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or applicati on, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of a ny information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of e x p o r t p e r t a i n i n g t o c u s t o m s a n d t a r i f f s , c u r r en c y e x c h a n g e , o r s t r a t e g i c m a t e r i a l s . * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, excep t with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * I t i s t h e r e s p o n s i b i l i t y o f t h e b uy e r o r d i s t r i b u t o r o f a n A K M p r o d u c t w h o d i s t r i b u t e s , disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0063-E-01 - 24 -
2002/07

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